Quad flat no leads package with locking feature

ABSTRACT

Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of the earlier U.S. UtilityPatent Application to Soon Wei Wang entitled “Quad Flat No Leads PackageWith Locking Feature,” application Ser. No. 15/230179, filed Aug. 5,2016, now pending, the disclosure of which is hereby incorporatedentirely herein by reference.

BACKGROUND 1. Technical Field

Aspects of this document relate generally to semiconductor packages,such as quad flat no leads and dual flat no leads packages.

2. Background

Quad flat no lead (QFN) and dual flat no lead (DFN) packages have bottomleads that are flush with the edges of the package. They are designed tobe directly solderable to a motherboard or other circuit board. QFN andDFN packages are singulated using processes like sawing which serve toseparate the leads of the package from the remainder of the lead frame.

SUMMARY

Implementations of semiconductor packages may include: a lead framehaving at least one corner lead, the at least one corner lead positionedwhere two edges of the package meet, and the at least one lead having ahalf etch on a first portion of the lead and a half etch on a secondportion of the lead. The first portion may extend internally into thepackage to create a mechanical mold compound lock between a moldcompound of the package and the lead, and the second portion may belocated on at least one of the two edges of the package.

Implementations of semiconductor packages may include one, all, or anyof the following:

The first portion may be a portion of the at least one corner lead thatdoes not contact a mounting surface of the semiconductor package.

The first portion of the lead is configured to have a space for couplinga wire bond thereto.

The semiconductor package may further include a second lead adjacent tothe at least one corner lead where the second lead and the at least onecorner lead have a lead pitch of at least 0.2 millimeters.

Implementations of semiconductor packages may include: a lead framehaving at least one lead that may be located on an edge of the package,where the at least one lead may have a half etch on a first portion ofthe lead and a half etch on a second portion of the lead and where thefirst portion may extend internally into the package to create amechanical mold compound lock between a mold compound and the lead. Thesecond portion of the lead may be located on the edge of the package.

Implementations of semiconductor packages may include one, all, or anyof the following:

The first portion may be a portion of the at least one lead that doesnot contact a mounting surface of the semiconductor package.

The first portion of the lead may be configured to have a space forcoupling a wire bond thereto.

The semiconductor package may further include a second lead adjacent tothe at least one lead where the second lead and the at least one leadhave a lead pitch of at least 0.2 millimeters.

Implementations of a semiconductor package may be manufactured usingimplementations of a method of making semiconductor packages. The methodmay include providing a lead frame including at least one leadpositioned at an edge of the package; etching one half of a firstportion of the at least one lead at an outer edge of the lead adjacentto the edge of the package; and etching one half of a second portion ofthe at least one lead at an inner edge of the lead opposite the outeredge. The first portion may be configured to mechanically lock with amold compound of the package and the first portion may not contact anyedge of the package.

Implementations of semiconductor packages may include one, all, or anyof the following:

The first portion may be a portion of the at least one lead that doesnot contact a mounting surface of the semiconductor package.

The first portion of the lead may be configured to have a space forcoupling a wire bond thereto.

The semiconductor package may further include a second lead adjacent tothe at least one lead where the second lead and the at least one leadhave a lead pitch of at least 0.2 millimeters.

The at least one lead may be a corner lead positioned where two edges ofthe packages meet.

The second portion may be located on at least one of the two edges ofthe package.

The foregoing and other aspects, features, and advantages will beapparent to those artisans of ordinary skill in the art from theDESCRIPTION and DRAWINGS, and from the CLAIMS.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations will hereinafter be described in conjunction with theappended drawings, where like designations denote like elements, and:

FIG. 1 is a view of a dual flat no leads package semiconductor package;

FIGS. 2A-2B are top views of a lead frame;

FIGS. 3A-3B is a bottom view of a lead frame;

FIG. 4A is a perspective view of a lead frame design;

FIG. 4B is a front view of the lead frame design from FIG. 4A;

FIG. 4C is a top view of a lead frame design from FIG. 4A;

FIGS. 5A-5D are top views of no lead frames after package sawing;

FIG. 6A is a perspective view of an implementation of a lead framedesign with leads on the edge of the package;

FIG. 6B is a front view of an implementation of a lead frame design fromFIG. 6A;

FIG. 6C is a top view of an implementation of a lead frame design fromFIG. 6A;

FIG. 6D is a perspective view of an implementation of a semiconductorpackage with an implementation of a lead frame design from FIG. 6A;

FIGS. 7A-7F are top views of implementations of a lead frame designhaving leads on the edge of the package after packaging sawing; and

FIGS. 8A-8B show a comparison of a lead frame package, FIG. 8A, and animplementation of a lead frame having leads on the edge of the package,FIG. 8B.

DESCRIPTION

This disclosure, its aspects and implementations, are not limited to thespecific components, assembly procedures or method elements disclosedherein. Many additional components, assembly procedures and/or methodelements known in the art consistent with the intended semiconductorpackage will become apparent for use with particular implementationsfrom this disclosure. Accordingly, for example, although particularimplementations are disclosed, such implementations and implementingcomponents may comprise any shape, size, style, type, model, version,measurement, concentration, material, quantity, method element, step,and/or the like as is known in the art for such semiconductor packagesand implementing components and methods, consistent with the intendedoperation and methods.

Referring to FIG. 1, a dual flat no leads (DFN) package 2 isillustrated. A top of the package 4 and a bottom of the package 6 areshown, the bottom being the surface of the package in which the leadsare exposed through mold compound. It can be seen that the design of thepackage keeps the bottom leads 8 away from the corners 10 of thepackage. Particular designs of QFNs and DFNs use a bottom half etch atthe lead tip to prevent lead drop off during sawing or, for LeadlessLand Grid Arrays, use of pre-plated lead frames. Pre-plated lead framesdepends on chemical locking between mold compound and the pre-platedleads to prevent lead drop off. These particular designs may restrictthe ability to make no lead packages smaller because additional spacemust be made available in the corners and edges of the package toprovide sufficient space to keep the leads from dropping off duringsingulation. As described more fully below, these particular designs ofthe leads are not robust enough to permit movement of the leads to theedge of the packages because of the saw offsets used in the singulationprocesses.

Referring now to FIG. 2A, a top view of a lead frame 12,pre-singulation, is illustrated. The perimeter of an individual package14 is outlined in the center of the lead frame 12. The corner leads 16of the package are designed away from the corners of the package toprevent the leads from falling off during the sawing process. Referringto FIG. 2B, an enlarged view of one of the corner leads 16 isillustrated. The minimum half etch on a first portion 18 is used forcompound locking. Referring to FIG. 3A, a bottom view of the lead frameshown in FIG. 2A is illustrated. As illustrated in FIG. 3B, leads 16 aredesigned to be away from the edges that form the package corner througha minimum half etch on the lead tip/second portion 20.

Referring to FIG. 4A, a perspective view of a no leads package 22 isillustrated. The leads 24 of the package are all located slightly awayfrom the package edge 26. Referring to FIG. 4B, a front view of thepackage 22 is illustrated. In this view, a minimum half etch on a firstportion 28 and a minimum half etch on a second portion 30 are visible.The first portion 28 and second portion 30 half etch are designed to aidin mold compound locking between the lead and the mold compound of thepackage. Referring to FIG. 4C, a top view of the package is illustratedshowing the minimum half etch on a first portion 28 and minimum halfetch on a second portion 30. As can be observed, particularly in FIGS.4A and 4C, the first portions 28 of the various leads are etched so thata side of the first portions still is located on a side of the package

Referring now to FIG. 5A-5D, no lead packages as illustrated in FIGS.4A-4C after sawing are illustrated. In FIG. 5A, there is no offset onthe saw. In FIG. 5B, the saw offset from standard position is 10microns. In FIG. 5C, the saw offset is 20 microns and it can be seenthat a corner lead 32 has fallen off during sawing due to insufficientlocking between the lead and the mold compound. In FIG. 5D, the sawoffset is 30 microns and again a corner lead 34 has dropped off due toinsufficient locking between the lead and the mold compound. Since thesesaw offsets are within the potential operating tolerances of singulationprocesses, the design of FIGS. 5A-5D is marginal, as it providesinsufficient mold locking to prevent lead drop off during sawing.

Referring now to FIG. 6A, a perspective view of an implementation ofsemiconductor package 36 having a lead frame having leads on the edge ofthe package is illustrated. At least one lead 38 is located on the edgeof the package 36—in other words, the metal of the lead is not offsetfrom the edge through mold compound, but is right on the edge. In otherimplementations, the at least one lead on the edge of the package is acorner lead positioned where two edges of the package meet, such as theleads to the right and left of the lead 38 in FIG. 6A. Referring to FIG.6B, a front view of an implementation of a semiconductor package 36 isillustrated. At least one corner lead 40 having a maximum half etch on afirst portion 42 and a maximum half etch on a second portion 44 isillustrated. The size of a maximum half etch as used herein is largerthan a minimum half etch but not so large that the etch reduces thespace 46 in FIG. 6C to prevent adequate area remaining for wire bonding.The first portion 42 of the lead extends internally into the package tocreate a mechanical mold compound lock between a mold compound of thepackage 36 and the lead 40. The mechanical mold compound lock mayincrease the robustness of the package. As can be seen in FIG. 6B, thefirst portion 42 of the lead does not contact the mounting surface ofthe semiconductor package. Also, no portion of the first portion 42 ofthe lead is located on an edge of the package, while the second portion44 of the lead 40 is a corner lead positioned on the two edges of thepackage.

Referring to FIG. 6C, a top view of an implementation of lead frame 36is illustrated. The first portion 42 of the lead 40 is configured tohave space 46 for coupling a wire, such as a wire bond, thereto. Thepackage 36 has a second lead 47 adjacent the at least one corner leadwhere the second lead 47 and the at least one corner lead 40 have a leadpitch/gap of at least 0.2 millimeters between them. As can be observed,the upper first portion of lead 47 also does not have any portion of itssurface that touches or is located on the edge of the package, while thelower second portion is located on the edge of the package.

Referring to FIG. 6D, an implementation of a semiconductor package 48 isillustrated in see through format where the mold compound is madeinvisible. As is illustrated, lead 50 is on the edge of the package 48and wirebonds are used to attached the first portions of the leads todie coupled to other leads within the package.

Referring to FIG. 7A-7F, the results of an experiment involving leadswith structures like those illustrated in FIGS. 6A-D are shown. Thephotographs are of the bottom side of the package after sawing. The sawoffset ranges are 0 m (FIG. 7A), 10 μm (FIG. 7B), 20 μm (FIG. 7C), 30 μm(FIG. 7D), 40 μm (FIG. 7E) and 50 μm (FIG. 7F). As can be seen in thefigure, no leads dropped off due to saw offset in all six of theexamples. This visually demonstrates an improvement over the lead frameexample illustrated in FIGS. 5C and 5D where the corner leads droppedoff at saw offsets of just 20 μm and 30 μm. The improved mold compoundlocking achieved by implementing a maximum half etch on a first portionnot located on an edge of the package and a maximum half etch on asecond portion located on the edge of the package illustrates a robustlead design even up to 50 μm of saw offset. This increase in processrobustness will allow for the leads to be placed at the edge of thepackage, rather than having to be offset.

Referring now to FIGS. 8A and 8B, a visual comparison of a twosemiconductor packages is illustrated. In FIG. 8A, a semiconductorpackage having leads designed away from the edge of the package isillustrated. As can be seen, there is a gap between the leads 56 and theedge of the package 58. Referring to FIG. 8B, in contrast, animplementation of semiconductor package having leads at/on the edge ofthe package is illustrated. With the leads placed at the edge of thepackage the package size can be decreased by at least 0.1 mm while stillmaintaining a minimum 0.2 mm lead gap/pitch between leads.

Method of semiconductor packages like those disclosed herein may beformed using implementations of a method of forming implementations ofsemiconductor packages. Method implementations may include providing alead frame having at least one lead positioned at an edge of thepackage. One half of a first portion of the at least one lead may beetched at an outer edge of the lead adjacent to the edge of the package.One half of a second portion of the at least one lead may be etched atan inner edge of the lead opposite the outer edge. The lead frame may beetched using chemical etching, dry etching, laser cutting, hard tooletching or any suitable method known in the art.

Furthermore, the materials used for the leads may be any of those usedfor leads and lead frames known in the art, including, by non-limitingexample, copper, copper alloys, silver, aluminum, any combinationthereof, and any other electrically conductive material. Furthermore,the leads may be coated with any number of other electrically conductivematerials, such as, by non-limiting example, silver, gold, nickel,platinum, palladium, tin, titanium, or any combination thereof. Also,the mold compounds used in various package implementations may be any ofa wide variety known, including epoxies, thermally conductive epoxies,resins, and the like.

In places where the description above refers to particularimplementations of semiconductor packages and implementing components,sub-components, methods and sub-methods, it should be readily apparentthat a number of modifications may be made without departing from thespirit thereof and that these implementations, implementing components,sub-components, methods and sub-methods may be applied to othersemiconductor packages.

What is claimed is:
 1. A method for forming a semiconductor package, themethod comprising: providing a lead frame comprising at least one leadpositioned at an outer edge of the package; etching one half of a firstportion of the at least one lead at an outer edge of the at least onelead adjacent to the outer edge of the package; and etching one half ofa second portion of the at least one lead at an inner edge of the atleast one lead opposite the outer edge of the at least one lead; whereinthe first portion is configured to mechanically lock with a moldcompound of the package; and wherein the second portion is a portion ofthe at least one lead that contacts a mounting surface of thesemiconductor package.
 2. The method of claim 1, wherein the mountingsurface extends to the outer edge of the package.
 3. The method of claim1, wherein the first portion of the at least one lead is configured tohave space for coupling a wire bond thereto.
 4. The method of claim 1,further comprising a second lead adjacent to the at least one lead wherethe second lead and the at least one lead have a lead pitch of at least0.2 millimeters.
 5. The method of claim 1, wherein the at least one leadis a corner lead positioned where two outer edges of the package meet.6. The method of claim 5, wherein the second portion is located on twoouter edges of the package.
 7. A method for forming a semiconductorpackage, the method comprising: providing a lead frame comprising acorner lead positioned at an outer edge of the package; etching one halfof a first portion of the corner lead at an outer edge of the cornerlead adjacent to the outer edge of the package; and etching one half ofa second portion of the corner lead at an inner edge of the corner leadopposite the outer edge of the corner lead; wherein the first portion isconfigured to mechanically lock with a mold compound of the package; andwherein the second portion extends to the outer edge of the package. 8.The method of claim 7, wherein the second portion forms a mountingsurface positioned where two outer edges of the package meet.
 9. Themethod of claim 7, wherein the first portion of the corner lead isconfigured to have space for coupling a wire bond thereto.
 10. Themethod of claim 7, further comprising a second lead adjacent to thecorner lead where the second lead and the corner lead have a lead pitchof at least 0.2 millimeters.
 11. The method of claim 7, wherein thecorner lead is positioned where two outer edges of the package meet. 12.The method of claim 11, wherein the second portion is located on twoouter edges of the package.
 13. A method for forming a semiconductorpackage, the method comprising: providing a lead frame comprising a leadpositioned where two outer edges of the package meet; etching one halfof a first portion of the lead at an outer edge of the lead adjacent toat least one of the two outer edges of the package; and etching one halfof a second portion of the lead at an inner edge of the lead oppositethe at least one outer edge of the lead; wherein the first portion isconfigured to mechanically lock with a mold compound of the package;wherein the second portion is a portion of the lead that contacts amounting surface of the semiconductor package; and wherein the mountingsurface extends to at least one of the two outer edges of the package.14. The method of claim 13, wherein the mounting surface extends to twoouter edges of the package.
 15. The method of claim 13, wherein thefirst portion of the lead is configured to have space for coupling awire bond thereto.
 16. The method of claim 13, further comprising asecond lead adjacent to the lead where the second lead and the at leastone lead have a lead pitch of at least 0.2 millimeters.
 17. The methodof claim 13, wherein the lead is a corner lead.
 18. The method of claim17, wherein the second portion is located on two outer edges of thepackage.